A modern application specific integrated circuit (ASIC) requires a significant amount of random access memory (RAM) to operate satisfactorily. In an example, for networking applications, the memory needs to be accessed at a high rate with low latency. Often, a single ASIC chip needs to read and write independently to multiple memory elements. One present solution to the need for ASIC memory access is to use dynamic RAM (DRAM) embedded in a logic process, so-called embedded DRAM or eDRAM, to locate memory near the logic that accesses it and to connect the memory to the logic using a wide bus. eDRAM memory is dense and, being on the same chip with the ASIC logic, allows dense, high-speed interconnections between the memory and the logic. eDRAM also avoids the slow, narrow, power-hungry interface entailed in connecting a logic die to separate DRAM dice through either packages and a printed circuit board (PCB) or in a side-by-side multi-chip module (MCM).
Embedded DRAM however presents a number of challenges. The additional processing steps to embed the memory with the logic adds cost and reduces yield. The embedded DRAM is not as dense as it is in a dedicated DRAM and it is less stable. In the case of some available embedded DRAM technologies, a stacked-capacitor deepens the first contact to a point at which it significantly increases its resistance and capacitance thus lowering the performance of the logic. Lastly, embedded DRAM technology is not widely available.
In integrated circuit (IC) technology, a circuit almost always performs better and costs less when it is built in a process designed for its function, so partitioning the system into separate logic and DRAM chips is attractive. The high parasitics of the connection between separate dice on a PCB or even an MCM substrate might be alleviated by stacking one die on the other. However, until recently, stacked dice have almost always been connected by wirebonding at their perimeters, which greatly limits the number and quality of the connections. For many communication system and networking chips, multiple wide logic to memory buses with low parasitics are desired.
Recently, interconnect technologies known as fine pitch through-silicon via (TSV) and metal-to-metal bonds have been developed to enable the fabrication of stacked dice having an area array interconnect in a “through-silicon stacking” (TSS) architecture. An area array interconnect using TSVs and metal-to-metal bonds provide physically short, low parasitic connections, to provide what can be referred to as “I/O-less on-chip access to off-chip technology.” Such through-silicon stacking allows the consideration of partitioning an IC device into separate logic and DRAM dice.
Advantages of through-silicon stacking of logic and DRAM over connecting them together on a PCB or MCM include, for example, lower power consumption and higher speed due to dramatically lower interconnect parasitics, interface simplification, wider, denser interface permitting higher data transfer rate and greater architectural flexibility, and less printed circuit board (PCB) area, which can also be a disadvantage with regard to heat removal.
Therefore, it would be desirable to have a way of developing an integrated circuit whose performance can be maximized through the availability of die stacking technologies.